DTIC ADA085078: Test Generation for Microprocessors pdf

DTIC ADA085078: Test Generation for Microprocessors

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The goal of this report is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by availability of a large variety of microprocessors. They differ widely in their organization, instruction repertoire, addressing modes, data storage and manipulation facilities, etc. In this report, a general graph-theoretic model for microprocessors is developed at the register transfer level. Any microprocessor can be easily modeled using information only about the instruction set and the functions performed by it. This information is easily available in the user’s manual. A fault model is developed on a functional level quite independent of the implementation details. The effects of faults in the fault model are investigated at the level of the graph-theoretic model.

Test generation procedures are proposed which take the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model. The complexity of the test sequences measured in terms of the number of instructions is given. Our effort in generating tests for a real microprocessor and evaluating their fault coverage is described. (Author

• Creator/s: Defense Technical Information Center
• Date: 5/1/1979
• Year: 1979
• Book Topics/Themes: DTIC Archive, Thatte, Satish Mukund, ILLINOIS UNIV AT URBANA-CHAMPAIGN COORDINATED SCIENCE LAB, *MICROPROCESSORS, *TEST METHODS, *COMPUTER ARCHITECTURE, MATHEMATICAL MODELS, TRANSFER FUNCTIONS, INFORMATION TRANSFER, THESES, GATES(CIRCUITS), USER NEEDS, DATA STORAGE SYSTEMS, FLIP FLOP CIRCUITS, INPUT OUTPUT MODELS, NETWORK FLOWS, ERROR DETECTION CODES, ADDRESSING

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