DTIC ADA159824: A Systolic Array Implementation of pdf

DTIC ADA159824: A Systolic Array Implementation of

More Book Details

Description of the Book:

A systolic array is a natural architecture for the implementation of a Reed-Solomon (RS) encoder and decoder. It possesses many of the properties desired for a special-purpose application: simple and regular design, concurrency, modular expansibility, fast response time, cost-effectiveness, and high reliability. As a result, it is very will suited for the simple and regular design essential for VLSI implementation. This thesis takes a modular approach to the design of a systolic array based RS encoder and decoder. Initially, the concept of systolic arrays is discussed followed by an introduction to finite field theory and Reed-Solomon error correction codes. Then it is shown how RS codes can be encoded and decoded with primitive shift registers and implemented using a systolic architecture. In this way, the reader can gain valuable insight and comprehension into how these entities are coalesced together to produced the overall implementation. Additional keywords: Systolic multipliers.

(Author

• Creator/s: Defense Technical Information Center
• Date: 6/1/1985
• Year: 1985
• Book Topics/Themes: DTIC Archive, McKenzie, S S, NAVAL POSTGRADUATE SCHOOL MONTEREY CA, *ERROR CORRECTION CODES, QUICK REACTION, COST EFFECTIVENESS, COMPUTER ARCHITECTURE, THESES, HIGH RELIABILITY, DECODERS, SHIFT REGISTERS

An excerpt captured from the PDF book